1. Field of the Invention
The present invention relates generally to BiCMOS integrated circuit devices and more particularly to a cascoded Non-Threshold Logic (NTL) based BiCMOS circuit arrangement with low power consumption and a multi-level logic function.
2. Description of the Prior Art
Due to the variety of applications in which semiconductor chips may be used, there are a number of logic families that are currently in use and available to circuit designers. Some of the families presently in use include transistor-transistor logic (TTL), diode-transistor logic (DTL), emitter-coupled logic (ECL) and metal oxide semiconductor logic (MOS).
Each logic family has specific advantageous properties as well as corresponding disadvantageous features. For example ECL logic is characterized in that it gives faster switching speeds than most other logic families. However, the standard ECL circuit dissipates a significant amount of power.
ECL circuits are able to function at high speed because the biases on the input transistors as well as the collector and emitter resistor ratios can be selected to avoid saturation. Since the delay associated with removing saturation-caused excess charge from the collector is avoided, the circuit has minimal switching delay. This low switching delay in combination with ECL's small voltage swings makes it one of the fastest technologies in use today. In addition to high speed, ECL provides a high fan out capability because of its emitter follower configuration.
On the other hand, the use of ECL is costly to designers in terms of power consumption. Since ECL functions by redirecting current instead of cutting it on and off, current through the emitter resistance is substantially constant regardless of the output state. This causes a very high power dissipation per gate in comparison with other technologies. As a result the number of gates which may be included on a chip is limited.
Designers using ECL have also been frustrated by the fact that ECL has been very difficult to interface with other logic families. This is especially true for ECL/MOS interfaces. Because of ECL's higher supply voltage requirements and elimination of transistor saturation, designers wishing to combine ECL with other technologies have been forced to include complex signal level conversion circuitry in the overall circuit.
Referring to FIG. 1, a prior art low-voltage ECL-based BiCMOS circuit 102 will be described. This circuit is also described in C. L. Chen, "2.5 V Bipolar/CMOS Circuits for 0.25 .mu.m BiCMOS Technology", IEEE Journal of Solid State Circuits, Vol. 27, No. 4, April 1992, pp. 485-491 which is hereby incorporated by reference. This circuit operates at its minimum supply voltage of three times the emitter to base turn on voltage (V.sub.be) or about 2.5 V. The ECL circuit is similar to a conventional ECL circuit in that it has resistor loads 122 and 124 and a current source controlled by a current mirror. The signal swing at the output 132 is one V.sub.be with a logical high being (V.sub.dd -V.sub.be) and a logical low being V.sub.be above ground.
This circuit is preferred over a conventional ECL circuit because it can operate using a 2.5 V CMOS supply and thus interface with CMOS circuitry relatively easily. In addition, since a minimum power supply is used, the relatively high power consumption of a standard ECL circuit is greatly reduced in the circuit represented in FIG. 1. Power consumption is also reduced in this circuit by terminating the pull-down NFET 126 in the emitter-follower to a diode 128.
The low-power ECL circuit 102, has a disadvantage in that it often has higher device counts than would be desirable. The inclusion of threshold elements in the circuit contributes to the high device count. Because a given function (in this case, the NOR function) takes more devices to perform, less logic can be fit into a given area and chip size must be increased to accommodate the same logic.
Another disadvantage of ECL which is inherent in the low-voltage ECL circuit of FIG. 1, is its limitation to a single level of logic. Cascoding of logic functions is not possible since each level requires the equivalent of one V.sub.be of supply voltage. In the low-voltage circuit of FIG. 1, the input transistor, load resistor and current source each use one V.sub.be thus allowing only one logic level.
Finally, the low-voltage ECL circuit of FIG. 1 still exhibits a relatively high power dissipation. Although the supply voltage has been reduced in the low-voltage circuit, the characteristic ECL constant current in the circuit still exists. As long as current is being redirected instead of cut off, the ECL circuit will be relatively power hungry.
FIG. 2 shows a prior art conventional non-threshold logic (NTL) circuit 202 which lowers the device count needed to perform a given function from that of ECL. While the ECL and NTL circuits in FIG. 1 and FIG. 2 are somewhat similar, a major difference is the fact that the reference transistor 110 coupled to the input transistors 112 and 114 in the ECL circuit 102 is not present in the NTL circuit 202. As a result, the voltage at the base 224 of the emitter follower transistor 220 immediately rises or falls when the input falls or rises, respectively. Thus, the delay in ECL attributable to the time it takes for the input signal to rise to V.sub.ref during pull-up, is not present in the NTL circuit of FIG. 2.
In an NTL circuit the input is not compared with a reference voltage as it is in ECL technology. In an ECL circuit, when the input level is above the reference level, a current flows through a load device and generates an output low level. On the other hand, when the input is below the reference level, the same current is redirected into a reference current branch. There is no voltage drop across the load device, and an output high level is generated.
By contrast, in an NTL circuit, there is no reference level or reference current branch. The high and low levels of an input signal vary the amount of current conducting in the load device. The difference in current results in a voltage difference across the load device and generates an output signal.
Because no reference voltage is required, NTL circuitry can be operated with a lower power supply than a conventional ECL circuit and it therefore dissipates less dc power than a conventional ECL circuit. In addition, because NTL does not require threshold logic, it has the advantage of smaller device counts as compared to conventional ECL technology. The current mirror which is used in ECL is not used in NTL and NTL, therefore, does not draw continuous current as does ECL.
The conventional NTL circuit is not without its drawbacks, however. There are two major problems encountered with NTL. First, due to the nature of the no-reference operation, even a small input variation induces a current change which can alter the output level. As a result, an NTL circuit is more sensitive to noise and input signal variation. Secondly, an NTL signal may degrade and diminish gradually if an input fails to reach its full signal level. For example, if an input signal swinging from a high level to a low level does not go low enough, the output high-level (assuming inverter or NOR logic) will be degraded from a desirable high level. This degraded signal will propagate through the circuit and will continuously worsen. In some situations, a signal may disappear completely.